GR-Tue-2 - Epitaxy of > 7 µm thick GaN drift layers on Si (111) for fully vertical power devices
1. GrowthYoussef Hamdaoui2, Sarad Thapa1, Sven Besendörfer3, Farid Medjdoub2, Elke Meissner3
1 Siltronic AG, München, Germany
2 CNRS IEMN, Villeneuve-d’Ascq, France
3 Fraunhofer Institute for Integrated Systems and Device Technology IISB, Erlangen, Germany
Abstract text
Vertical GaN-on-Si(111) power devices potentially offer significant advantages over their lateral counterpart, including higher threshold voltage, increased current density, and higher breakdown voltage without compromising the device size [1]. Using silicon as a substrate is cost-effective due to its large diameter and low cost, making it appealing for industrial use. Moreover, the Si substrate can be locally removed under the active area of the device to realize a fully vertical current flow [1]. However, challenges remain in the epitaxy of sufficiently thick GaN drift layers on Si to facilitate high breakdown voltages due to the significant thermal and lattice mismatch inherent in the heteroepitaxial system.
In this work, GaN-based PN structures with drift layers thicker than 7 µm, capable of achieving 1200 V breakdown voltages, are grown on 6” Si(111) substrates using an industrial metal-organic chemical vapor deposition reactor. Utilizing a novel buffer based on an AlN/AlGaN superlattice that incorporates islands with optimized geometry, the threading dislocation density is drastically reduced. This, in turn, allows sufficiently compressive stress to be maintained in the subsequent active GaN layers during growth, compensating for the thermal mismatch with the substrate [2]. It was found that the geometry of the islands, which form on V-pits present in the AlN nucleation layer, can be effectively controlled by adjusting the growth temperature. Leveraging this buffer concept, crack-free GaN-based PN structures with a drift layer thickness of 7.4 μm (10 μm total thickness) on 6" Si(111) substrates were achieved, with an absolute wafer bow < 50 μm and a low threading dislocation density of 3.6 x 108 cm-2 [3]. Electrical characterization of fully vertical PN diodes on this wafer revealed a 1220 V non-destructive breakdown with avalanche capability, accompanied by a low Ron,sp ~ 0.5 mΩcm2 [4]. These results pave the way for high-performance GaN-on-Si vertical power devices operating in the kilovolt range.
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[2] S. Michler, et al., Physica Status Solidi (b), 2400019 (2024).
[3] S. Michler, et al., Physica Status Solidi (a), 2400544 (2024).
[4] Y. Hamdaoui, et al., IEEE Transactions on Electron Devices, 10758680 (2024).